The MyHDL manual
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6.3.7 Choice of encoding
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6.3 Features
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6.3.9 Support for ROM
6.3.8 Support for RAM inference
Certain synthesis tools can map Verilog memories to RAM structures. To support this interesting feature, the Verilog converter maps lists of signals to Verilog memories.
The MyHDL manual
Previous:
6.3.7 Choice of encoding
Up:
6.3 Features
Next:
6.3.9 Support for ROM
Release 0.5.1, documentation updated on May 1, 2006.
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