6.3.10 Support for signed arithmetic
In MyHDL, working with negative numbers is trivial: one just uses
intbv objects with negative values.
By contrast, negative numbers are tricky in Verilog. The language
makes a difference between an unsigned and a signed representation,
and the user has to declare signed variables explicitly. When the two
representations are mixed in an expression, all operands are
interpreted as unsigned, which typically leads to unexpected results.
The Verilog converter handles negative intbv objects by using
a signed Verilog representation. Also, it automatically performs sign
extension and casting to a signed representation when unsigned numbers
are used in a mixed expression. In this way, it automates a task which
is notoriously hard to get right in Verilog directly.
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