6.6.6 ROM inference

Some synthesis tools can infer a ROM memory from a case statement. The Verilog converter can perform the expansion into a case statement automatically, based on a higher level description. The ROM access is described in a single line, by indexing into a tuple of integers. The tuple can be described manually, but also by programmatical means. Note that a tuple is used instead of a list to stress the read-only character of the memory.

The following example illustrates this functionality. ROM access is described as follows:

def rom(dout, addr, CONTENT):
                                                                                
    @always_comb
    def read():
        dout.next = CONTENT[int(addr)]
                                                                                
    return read

The ROM content is described as a tuple of integers. When the ROM content is defined, the conversion can be performed:

CONTENT = (17, 134, 52, 9)
dout = Signal(intbv(0)[8:])
addr = Signal(intbv(0)[4:])
                                                                                
toVerilog(rom, dout, addr, CONTENT)

The Verilog output code is as follows:

module rom (
    dout,
    addr
);
                                                                                
output [7:0] dout;
reg [7:0] dout;
input [3:0] addr;
                                                                       
always @(addr) begin: _rom_read
    // synthesis parallel_case full_case
    case (addr)
        0: dout <= 17;
        1: dout <= 134;
        2: dout <= 52;
        default: dout <= 9;
    endcase
end
                                                                                
endmodule

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