The MyHDL manual

Previous: The MyHDL manual Up: The MyHDL manual Next: 1. Background information

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Contents

• 1. Background information
  • 1.1 Prerequisites
  • 1.2 A small tutorial on generators
  • 1.3 About decorators
• 2. Introduction to MyHDL
  • 2.1 A basic MyHDL simulation
  • 2.2 Signals, ports, and concurrency
  • 2.3 Parameters and hierarchy
  • 2.4 Bit oriented operations
    • 2.4.1 Bit indexing
    • 2.4.2 Bit slicing
  • 2.5 Some remarks on MyHDL and Python
  • 2.6 Summary and perspective
• 3. Modeling techniques
  • 3.1 Structural modeling
    • 3.1.1 Conditional instantiation
    • 3.1.2 Arrays of instances
    • 3.1.3 Inferring the list of instances
  • 3.2 RTL modeling
    • 3.2.1 Combinatorial logic
    • 3.2.2 Sequential logic
    • 3.2.3 Finite State Machine modeling
  • 3.3 High level modeling
    • 3.3.1 Modeling with bus-functional procedures
    • 3.3.2 Modeling memories with built-in types
    • 3.3.3 Modeling errors using exceptions
    • 3.3.4 Object oriented modeling
• 4. Unit testing
  • 4.1 Introduction
  • 4.2 The importance of unit tests
  • 4.3 Unit test development
    • 4.3.1 Defining the requirements
    • 4.3.2 Writing the test first
    • 4.3.3 Test-driven implementation
    • 4.3.4 Changing requirements
• 5. Co-simulation with Verilog and VHDL
  • 5.1 Introduction
  • 5.2 The HDL side
  • 5.3 The MyHDL side
  • 5.4 Restrictions
    • 5.4.1 Only passive HDL can be co-simulated
    • 5.4.2 Race sensitivity issues
  • 5.5 Implementation notes
    • 5.5.1 Icarus Verilog
    • 5.5.2 Cver
    • 5.5.3 Other Verilog simulators
    • 5.5.4 Interrupted system calls
    • 5.5.5 VHDL
• 6. Conversion to Verilog
  • 6.1 Introduction
  • 6.2 Solution description
  • 6.3 Features
    • 6.3.1 The design is converted after elaboration
    • 6.3.2 The structural description can be arbitrarily complex and hierarchical
    • 6.3.3 Generators are mapped to Verilog always or initial blocks
    • 6.3.4 The Verilog module interface is inferred from signal usage
    • 6.3.5 Function calls are mapped to a unique Verilog function or task call
    • 6.3.6 If-then-else structures may be mapped to Verilog case statements
    • 6.3.7 Choice of encoding schemes for enumeration types
    • 6.3.8 Support for RAM inference
    • 6.3.9 Support for ROM memory
    • 6.3.10 Support for signed arithmetic
    • 6.3.11 Support for user-defined Verilog code
  • 6.4 The convertible subset
    • 6.4.1 Introduction
    • 6.4.2 Coding style
    • 6.4.3 Supported types
    • 6.4.4 Supported statements
    • 6.4.5 Supported built-in functions
    • 6.4.6 Excluding code from conversion
  • 6.5 Methodology notes
    • 6.5.1 Simulation
    • 6.5.2 Conversion output verification
    • 6.5.3 Assignment issues
  • 6.6 Converter usage
    • 6.6.1 A small sequential design
    • 6.6.2 A small combinatorial design
    • 6.6.3 A hierarchical design
    • 6.6.4 Optimizations for finite state machines
    • 6.6.5 RAM inference
    • 6.6.6 ROM inference
    • 6.6.7 User-defined Verilog code
  • 6.7 Known issues
• 7. Reference
  • 7.1 Simulation
    • 7.1.1 The Simulation class
    • 7.1.2 Simulation support functions
    • 7.1.3 Waveform tracing
  • 7.2 Modeling
    • 7.2.1 The Signal class
    • 7.2.2 MyHDL generators and trigger objects
    • 7.2.3 Decorator functions
    • 7.2.4 The intbv class
    • 7.2.5 Miscellaneous modeling support functions
  • 7.3 Co-simulation
    • 7.3.1 MyHDL
    • 7.3.2 Verilog
    • 7.3.3 VHDL
  • 7.4 Conversion to Verilog
    • 7.4.1 Conversion
    • 7.4.2 User-defined Verilog code
• Index

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The MyHDL manual

Previous: The MyHDL manual Up: The MyHDL manual Next: 1. Background information

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Release 0.5.1, documentation updated on May 1, 2006.