The MyHDL manual

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6.3 Features

• 6.3.1 The design is converted after elaboration
• 6.3.2 The structural description can be arbitrarily complex and hierarchical
• 6.3.3 Generators are mapped to Verilog always or initial blocks
• 6.3.4 The Verilog module interface is inferred from signal usage
• 6.3.5 Function calls are mapped to a unique Verilog function or task call
• 6.3.6 If-then-else structures may be mapped to Verilog case statements
• 6.3.7 Choice of encoding schemes for enumeration types
• 6.3.8 Support for RAM inference
• 6.3.9 Support for ROM memory
• 6.3.10 Support for signed arithmetic
• 6.3.11 Support for user-defined Verilog code

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The MyHDL manual

Previous: 6.2 Solution description Up: 6. Conversion to Verilog Next: 6.3.1 The design is

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Release 0.5.1, documentation updated on May 1, 2006.