The MyHDL manual

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6.1 Introduction

MyHDL supports the automatic conversion of implementation-oriented MyHDL code to Verilog code. This feature provides a direct path from Python to an FPGA or ASIC implementation.

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The MyHDL manual

Previous: 6. Conversion to Verilog Up: 6. Conversion to Verilog Next: 6.2 Solution description

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Release 0.5.1, documentation updated on May 1, 2006.