6.7 Known issues
- Verilog integers are 32 bit wide
- Usually, Verilog integers are 32 bit wide. In contrast, Python is
moving toward integers with undefined width. Python int
and long variables are mapped to Verilog integers; so for values
wider than 32 bit this mapping is incorrect.
- Synthesis pragmas are specified as Verilog comments.
- The recommended
way to specify synthesis pragmas in Verilog is through attribute
lists. However, the Icarus simulator doesn't support them
for
case statements (to specify parallel_case and
full_case pragmas). Therefore, the old
but deprecated method of synthesis pragmas in Verilog comments
is still used.
- Inconsistent place of the sensitivity list inferred from
always_comb.
- The semantics of
always_comb, both in Verilog and MyHDL, is to
have an implicit sensitivity list at the end of the code. However, this
may not be synthesizable. Therefore, the inferred sensitivity list is
put at the top of the corresponding always block.
This may cause inconsistent behavior at the start of the
simulation. The workaround is to create events at time 0.
- Non-blocking assignments to task arguments don't work.
- Non-blocking (signal) assignments to task arguments don't work
for an as yet unknown reason.
About this document
