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The MyHDL manual |  |
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The MyHDL manual | |
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Type intbv is likely to be the workhorse for synthesizable modeling in MyHDL. An intbv instance behaves like a (mutable) integer whose individual bits can be accessed and modified. Also, it is possible to constrain its set of values. In addition to error checking, this makes it possible to infer a bit width, which is required for implementation.
In Verilog, an intbv instance will be mapped to a reg
with an appropriate width. As noted before, it is not possible
to modify its value using name assignment. In the following, we
will show how it can be done instead. Consider:
a = intbv(0)[8:]
This is an intbv object with initial value 0 and
bit width 8. The change its value to 5, we can use
slice assignment:
a[8:] = 5
The same can be achieved by leaving the bit width unspecified, which has the meaning to change ``all'' bits:
a[:] = 5
Often the new value will depend on the old one. For example, to increment an intbv with the technique above:
a[:] = a + 1
Python also provides augmented assignment operators, which can be used to implement in-place operations. These are supported on intbv objects and by the converter, so that the increment can also be done as follows:
a += 1
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The MyHDL manual | |
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