6.5.2 Conversion output verification
It is always prudent to verify the converted Verilog output.
To make this task easier, the converter also generates a
test bench that makes it possible to simulate the Verilog
design using the Verilog co-simulation interface. This
permits to verify the Verilog code with the same test
bench used for the MyHDL code. This is also how
the Verilog converter development is being verified.
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