6.4.4 Supported statements
The following is a list of the statements that are supported by the
Verilog converter, possibly qualified with restrictions
or usage notes.
- break
- continue
- def
- for
- The only supported iteration scheme is iterating through sequences of
integers returned by built-in function range or MyHDL function downrange. The optional else clause is
not supported.
- if
- if, elif, and else clauses
are fully supported.
- pass
- print
- When printing an interpolated string, the format specifiers are copied
verbatim to the Verilog output. Printing to a file (with syntax
'»') is not supported.
- raise
- This statement is mapped to Verilog statements
that end the simulation with an error message.
- return
- yield
- The yielded expression can be a signal, a signal edge
as specified by MyHDL functions posedge
or negedge, or a tuple of signals and
edge specifications.
- while
- The optional else
clause is not supported.
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