6.4.3 Supported types

The most important restriction regards object types. Verilog is an almost typeless language, while Python is strongly (albeit dynamically) typed. The converter has to infer the types of names used in the code, and map those names to Verilog variables.

Only a limited amount of types can be converted. Python int and long objects are mapped to Verilog integers. All other supported types are mapped to Verilog regs (or wires), and therefore need to have a defined bit width. The supported types are the Python bool type, the MyHDL intbv type, and MyHDL enumeration types returned by function enum. The latter objects can also be used as the base object of a Signal.

intbv objects must be constructed so that a bit width can be inferred. This can be done by specifying minimum and maximum values, e.g. as follows:

index = intbv(0, min=MIN, max=MAX)

The Verilog converter supports intbv objects that can take negative values.

Alternatively, a slice can be taken from an intbv object as follows:

index = intbv(0)[N:]

Such as slice returns a new intbv object, with minimum value 0 , and maximum value 2**N.

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