The MyHDL manual

Previous: 5.5.5 VHDL Up: The MyHDL manual Next: 6.1 Introduction

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6. Conversion to Verilog

• 6.1 Introduction
• 6.2 Solution description
• 6.3 Features
  • 6.3.1 The design is converted after elaboration
  • 6.3.2 The structural description can be arbitrarily complex and hierarchical
  • 6.3.3 Generators are mapped to Verilog always or initial blocks
  • 6.3.4 The Verilog module interface is inferred from signal usage
  • 6.3.5 Function calls are mapped to a unique Verilog function or task call
  • 6.3.6 If-then-else structures may be mapped to Verilog case statements
  • 6.3.7 Choice of encoding schemes for enumeration types
  • 6.3.8 Support for RAM inference
  • 6.3.9 Support for ROM memory
  • 6.3.10 Support for signed arithmetic
  • 6.3.11 Support for user-defined Verilog code
• 6.4 The convertible subset
  • 6.4.1 Introduction
  • 6.4.2 Coding style
  • 6.4.3 Supported types
  • 6.4.4 Supported statements
  • 6.4.5 Supported built-in functions
  • 6.4.6 Excluding code from conversion
• 6.5 Methodology notes
  • 6.5.1 Simulation
  • 6.5.2 Conversion output verification
  • 6.5.3 Assignment issues
    • 6.5.3.1 Name assignment in Python
    • 6.5.3.2 Signal assignment
    • 6.5.3.3 intbv objects
• 6.6 Converter usage
  • 6.6.1 A small sequential design
  • 6.6.2 A small combinatorial design
  • 6.6.3 A hierarchical design
  • 6.6.4 Optimizations for finite state machines
  • 6.6.5 RAM inference
  • 6.6.6 ROM inference
  • 6.6.7 User-defined Verilog code
• 6.7 Known issues

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The MyHDL manual

Previous: 5.5.5 VHDL Up: The MyHDL manual Next: 6.1 Introduction

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Release 0.5.1, documentation updated on May 1, 2006.