The MyHDL manual

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5.5.2 Cver

MyHDL co-simulation is supported with the open source Verilog simulator Cver. The PLI module is based on the one for Icarus and basically has the same functionality. Only some cosmetic modifications were required.

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The MyHDL manual

Previous: 5.5.1.2 Passive Verilog check Up: 5.5 Implementation notes Next: 5.5.3 Other Verilog simulators

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Release 0.5.1, documentation updated on May 1, 2006.