The MyHDL manual

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5.5.1.2 Passive Verilog check

As explained before, co-simulated Verilog should not contain delay statements. Ideally, there should be a run-time check to flag non-compliant code. However, there is currently no such check in the Icarus module.

The check can be written using the cbNextSimTime VPI callback in Verilog. However, Icarus 0.7 doesn't support this callback. In the meantime, support for it has been added to the Icarus development branch. When Icarus 0.8 is released, a check will be added.

In the mean time, just don't do this. It may appear to ``work'' but it really won't as events will be missed over the co-simulation interface.

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The MyHDL manual

Previous: 5.5.1.1 Delta cycle implementation Up: 5.5.1 Icarus Verilog Next: 5.5.2 Cver

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Release 0.5.1, documentation updated on May 1, 2006.