The MyHDL manual

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5.5 Implementation notes

This section requires some knowledge of PLI terminology.

Enabling a simulator for co-simulation requires a PLI module written in C. In Verilog, the PLI is part of the ``standard''. However, different simulators implement different versions and portions of the standard. Worse yet, the behavior of certain PLI callbacks is not defined on some essential points. As a result, one should plan to write or at least customize a specific PLI module for any simulator. The release contains a PLI module for the open source Icarus and Cver simulators.

This section documents the current approach and status of the PLI module implementation and some reflections on future implementations.

• 5.5.1 Icarus Verilog
  • 5.5.1.1 Delta cycle implementation
  • 5.5.1.2 Passive Verilog check
• 5.5.2 Cver
• 5.5.3 Other Verilog simulators
• 5.5.4 Interrupted system calls
• 5.5.5 VHDL

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The MyHDL manual

Previous: 5.4.2 Race sensitivity issues Up: 5. Co-simulation with Verilog Next: 5.5.1 Icarus Verilog

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Release 0.5.1, documentation updated on May 1, 2006.