The MyHDL manual

Previous: 5. Co-simulation with Verilog Up: 5. Co-simulation with Verilog Next: 5.2 The HDL side

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5.1 Introduction

One of the most exciting possibilities of MyHDL is to use it as a hardware verification language (HVL). A HVL is a language used to write test benches and verification environments, and to control simulations.

Nowadays, it is generally acknowledged that HVLs should be equipped with modern software techniques, such as object orientation. The reason is that verification it the most complex and time-consuming task of the design process. Consequently, every useful technique is welcome. Moreover, test benches are not required to be implementable. Therefore, unlike with synthesizable code, there are no constraints on creativity.

Technically, verification of a design implemented in another language requires co-simulation. MyHDL is enabled for co-simulation with any HDL simulator that has a procedural language interface (PLI). The MyHDL side is designed to be independent of a particular simulator, On the other hand, for each HDL simulator a specific PLI module will have to be written in C. Currently, the MyHDL release contains a PLI module for two Verilog simulators: Icarus and Cver.

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The MyHDL manual

Previous: 5. Co-simulation with Verilog Up: 5. Co-simulation with Verilog Next: 5.2 The HDL side

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Release 0.5.1, documentation updated on May 1, 2006.