2.6 Summary and perspective
Here is an overview of what we have learned in this chapter:
- Generators are the basic building blocks of MyHDL models. They
provide the way to model massive concurrency and sensitiviy lists.
- MyHDL provides decorators that create useful generators from local functions.
- Hardware structure and hierarchy is described with classic Python functions.
Signal objects are used to communicate between concurrent generators.
intbv objects are used to describe bit-oriented operations.
- A
Simulation object is used to simulate MyHDL models.
These concepts are sufficient to start describing and simulating MyHDL models.
However, there is much more to MyHDL. Here is an overview of what can
be learned from the following chapters:
- MyHDL supports sophisticated and high level modeling techniques.
This is described in Chapter 3
- MyHDL enables the use of modern software verfication techniques,
such as unit testing, on hardware designs. This is the topic of
Chapter 4.
- It is possible to co-simulate MyHDL models with other HDL
languages such as Verilog and VHDL. This is described in
Chapter 5.
- Last but not least, MyHDL models can be converted to
Verilog, providing a path to a silicon implementation. This
is the topic of Chapter 6.
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