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7.4.1 Conversion

toVerilog(

func [, *args][, **kwargs])

Converts a MyHDL design instance to equivalent Verilog code, and also generates a test bench to verify it. func is a function that returns an instance. toVerilog() calls func under its control and passes *args and **kwargs to the call.

The return value is the same as would be returned by the call func(*args, **kwargs). It should be assigned to an instance name.

The top-level instance name and the basename of the Verilog output filename is func.func_name by default.

For more information about the restrictions on convertible MyHDL code, see section 6.4 in Chapter 6.

The toVerilog callable has the following attribute:

name

This attribute is used to overwrite the default top-level instance name and the basename of the Verilog output filename.

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The MyHDL manual

Previous: 7.4 Conversion to Verilog Up: 7.4 Conversion to Verilog Next: 7.4.2 User-defined Verilog code

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Release 0.5.1, documentation updated on May 1, 2006.