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The MyHDL manual |  |
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A user can insert user-defined code in the Verilog output
by using the __verilog__ hook.
__verilog__ hook variable specifies user-defined code that
should be used instead of converted code for that function. The
user-defined code should be a Python format string that uses keys to
refer to the variables that should be interpolated in the string. Any
variable in the function context can be referred to.
Note that this hook cannot be used inside generator functions or decorated local functions, as these are not elaborated.
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The MyHDL manual | |
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