The MyHDL manual

Previous: 7.3.1 MyHDL Up: 7.3 Co-simulation Next: 7.3.3 VHDL

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7.3.2 Verilog

$to_myhdl(

arg, [, arg ...])

Task that defines which signals (regs & nets) should be read by the MyHDL simulator. This task should be called at the start of the simulation.

$from_myhdl(

arg, [, arg ...])

Task that defines which signals should be driven by the MyHDL simulator. In Verilog, only regs can be specified. This task should be called at the start of the simulation.

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The MyHDL manual

Previous: 7.3.1 MyHDL Up: 7.3 Co-simulation Next: 7.3.3 VHDL

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Release 0.5.1, documentation updated on May 1, 2006.