The MyHDL manual

Contents:

• Overview

• Background information
  • Prerequisites
  • A small tutorial on generators
  • About decorators

• Introduction to MyHDL
  • A basic MyHDL simulation
  • Signals, ports, and concurrency
  • Parameters and hierarchy
  • Bit oriented operations
  • Some concluding remarks on MyHDL and Python
  • Summary and perspective

• Modeling techniques
  • Structural modeling
  • RTL modeling
  • High level modeling

• Unit testing
  • Introduction
  • The importance of unit tests
  • Unit test development

• Co-simulation with Verilog
  • Introduction
  • The HDL side
  • The MyHDL side
  • Restrictions
  • Implementation notes

• Conversion to Verilog and VHDL
  • Introduction
  • Solution description
  • Features
  • The convertible subset
  • Conversion of lists of signals
  • Assignment issues
  • Excluding code from conversion
  • User-defined code
  • Template transformation
  • Conversion output verification by co-simulation
  • Conversion of test benches
  • Methodology notes
  • Known issues

• Conversion examples
  • Introduction
  • A small sequential design
  • A small combinatorial design
  • A hierarchical design
  • Optimizations for finite state machines
  • RAM inference
  • ROM inference
  • User-defined code

• Reference
  • Simulation
  • Modeling
  • Co-simulation
  • Conversion to Verilog and VHDL
  • Conversion output verification