- MyHDL by Example
FPGA Synthesis Report
Release 8.1.02i - xst I.26
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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Reading design: StopWatch.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "StopWatch.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "StopWatch"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : StopWatch
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Write Timing Constraints : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
lso : StopWatch.lso
Read Cores : YES
cross_clock_analysis : NO
verilog2001 : YES
safe_implementation : No
Optimize Instantiated Primitives : NO
use_clock_enable : Yes
use_sync_set : Yes
use_sync_reset : Yes
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "/home/jand/dev/myhdl/example/cookbook/stopwatch/StopWatch.v" in library work
Module <StopWatch> compiled
No errors in compilation
Analysis of file <"StopWatch.prj"> succeeded.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <StopWatch>.
Module <StopWatch> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <StopWatch>.
Related source file is "/home/jand/dev/myhdl/example/cookbook/stopwatch/StopWatch.v".
Found 16x7-bit ROM for signal <$n0007> created at line 68.
Found 16x7-bit ROM for signal <$n0008> created at line 84.
Found 16x7-bit ROM for signal <$n0009> created at line 100.
Found 7-bit register for signal <tenths_led>.
Found 7-bit register for signal <ones_led>.
Found 7-bit register for signal <tens_led>.
Found 1-bit register for signal <_StopWatch_timecount_inst_logic/counting>.
Found 1-bit register for signal <_StopWatch_timecount_inst_logic/seen>.
Found 4-bit up counter for signal <ones>.
Found 4-bit up counter for signal <tens>.
Found 4-bit up counter for signal <tenths>.
Summary:
inferred 3 ROM(s).
inferred 3 Counter(s).
inferred 23 D-type flip-flop(s).
Unit <StopWatch> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 3
16x7-bit ROM : 3
# Counters : 3
4-bit up counter : 3
# Registers : 5
1-bit register : 2
7-bit register : 3
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# ROMs : 3
16x7-bit ROM : 3
# Counters : 3
4-bit up counter : 3
# Registers : 23
Flip-Flops : 23
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s100e.nph' in environment /home/jand/Xilinx.
Optimizing unit <StopWatch> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block StopWatch, actual ratio is 2.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : StopWatch.ngr
Top Level Output File Name : StopWatch
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 24
Cell Usage :
# BELS : 41
# INV : 3
# LUT2 : 2
# LUT3 : 23
# LUT3_D : 1
# LUT4 : 10
# LUT4_L : 2
# FlipFlops/Latches : 35
# FDC : 1
# FDCE : 13
# FDR : 18
# FDS : 3
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 23
# IBUF : 2
# OBUF : 21
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 22 out of 960 2%
Number of Slice Flip Flops: 35 out of 1920 1%
Number of 4 input LUTs: 38 out of 1920 1%
Number of bonded IOBs: 24 out of 66 36%
Number of GCLKs: 1 out of 24 4%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clock | BUFGP | 35 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 4.809ns (Maximum Frequency: 207.956MHz)
Minimum input arrival time before clock: 5.338ns
Maximum output required time after clock: 4.105ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
Clock period: 4.809ns (frequency: 207.956MHz)
Total number of paths / destination ports: 197 / 69
-------------------------------------------------------------------------
Delay: 4.809ns (Levels of Logic = 2)
Source: tenths_3 (FF)
Destination: tens_0 (FF)
Source Clock: clock rising
Destination Clock: clock rising
Data Path: tenths_3 to tens_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 11 0.514 1.124 tenths_3 (tenths_3)
LUT4:I0->O 1 0.612 0.684 _n0017118 (N251)
LUT4:I3->O 4 0.612 0.779 _n0017130 (_n0017)
FDCE:CE 0.483 tens_0
----------------------------------------
Total 4.809ns (2.221ns logic, 2.588ns route)
(46.2% logic, 53.8% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset: 5.338ns (Levels of Logic = 3)
Source: startstop (PAD)
Destination: tens_0 (FF)
Destination Clock: clock rising
Data Path: startstop to tens_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.931 startstop_IBUF (startstop_IBUF)
LUT2:I0->O 2 0.612 0.814 _n001011 (_n0010)
LUT4:I1->O 4 0.612 0.779 _n0017130 (_n0017)
FDCE:CE 0.483 tens_0
----------------------------------------
Total 5.338ns (2.813ns logic, 2.525ns route)
(52.7% logic, 47.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
Total number of paths / destination ports: 21 / 21
-------------------------------------------------------------------------
Offset: 4.105ns (Levels of Logic = 1)
Source: tenths_led_6 (FF)
Destination: tenths_led<6> (PAD)
Source Clock: clock rising
Data Path: tenths_led_6 to tenths_led<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.514 0.681 tenths_led_6 (tenths_led_6)
OBUF:I->O 2.910 tenths_led_6_OBUF (tenths_led<6>)
----------------------------------------
Total 4.105ns (3.424ns logic, 0.681ns route)
(83.4% logic, 16.6% route)
=========================================================================
CPU : 7.77 / 7.90 s | Elapsed : 11.00 / 14.00 s
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Total memory usage is 91176 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
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