Often Signals as seperate entities are not needed.

Assume we have a functional block datasource and a block datasink.

line = Signal(bool(0))
 
datasource(line)
datasink(line)

In classic myhdl you don't know about the signal direction without inspecting the source codes of datassource and datasink. In more complex designs it is also difficult to follow the signal path itself.

The following is an object oriented approach which avoids the signal definition in the top level code.

datasink.input = datasource.output

In case of only one output of the source block the syntax will be even simpler.

datasink(datasource)

Also chains are possible

datasink(dataprocessor(datasource))

 
class ClockGenerator(Block):
 
    output = Signal(bool())
 
    def __init__(self,period=2):
        self.period = period
        Block.__init__(self,*args,**kwargs)
 
    @instance
    def clockgen(self):
        while(1):
            yield delay(self.period//2)
            self.output = not self.output

class And(Block):
 
    output = Signal(bool())
 
    @always_comb
    def logic(self):
        self.output = self.a and self.b

class ToggleFF(Block):
 
    q = Signal(bool(0))
    output = q
                           # Input a is not defined at the time we are instantiating the class. 
    @always("a.posedge")   # Therefore we use the string.
    def toggleff(self):
        self.q = not self.q

clockgen = ClockGenerator(2)
tff = ToggleFF()
and_gate = And(clockgen, tff)

Or:

and_gate = And(
               ClockGenerator(period=2),
               ToggleFF()
               )

Or even:

and_gate = ClockGenerator(period=2) & ToggleFF()

• No signal definition neccessary in top level design
• Every signal of the functional subblock can be accessed from top level without source code modification of the subblock