My Examples and Projects

The following are projects that are mature but could be under development as well (always can find changes or features to add). These projects have been used by me or others. If you have issues or questions with the following projects feel free to post questions to the MyHDL newsgroup

• Configurable CIC Filter
• Recursive FFT
• MyHDL Fixed-Point Object
• USB FPGA Development Boards

The following are projects that I started but might have gone stale or just haven't had time to work more on them. These are use/preview at your own risk. The state of these projects might be too poor for some to handle. More than likely these projects will not work out of the box and will require some investigation. I thought it was useful to post these projects even know they are incomplete and *non-functional*. The wiki is a convenient spot to document progress on the projects which makes it easier to pick up when I do have time to work on them. These projects are products of sleepless nights are rainy Saturdays.

• MyHDL implementation of the ZPU processor
• MyHDL implementation of Gnu Radio USRP Verilog
• MyHDL Open Cores
• Using Python Dictionaries to Define Registers
• DSPSYS Simple DSP Testbenches

• MEP: List of Signals
• MEP: Signal Struct
• mep_free_var

• My FAQs
• MyHDL Performance Comparison intbv return types