From Python to silicon
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users:cfelton:projects:examples
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m1d5r0vhdl
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gciccomplete
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Cordic Calculations
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Examples
Welcome to MyHDL
Users & Projects
Thomas Traber
How to connect eispice and MyHDL
Cordic Calculations
Sine Wave Generator using Sigma Delta DAC
Cosimulation using Quartus Simulator
Interactive Simulation with IPython
Christopher L. Felton
Configurable CIC Filter
Recursive FFT
MyHDL Fixed-Point Object
USB FPGA Development Boards
Guenter Dannoritzer
Constellation Encoder
Complex Math
Rounding
FT245R Interface
George Pantazopoulos
To the memory of George
George's personal page
PhoenixSID 65x81
DSX1000 ΔΣ DAC Core
LFSR6581 RNG
Examples
WIP
users/cfelton/projects/examples.txt · Last modified: 2009/08/19 07:54 by cfelton
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