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       <dc:date>2010-07-31T16:44:13-05:00</dc:date>
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        <title>MyHDL</title>
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        <dc:date>2010-07-16T07:53:00-05:00</dc:date>
        <dc:creator>Guenter Dannoritzer</dc:creator>
        <title>Round-to-even-on-tie - Small rewording; fixed typo</title>
        <link>http://www.myhdl.org/doku.php/projects:rounding?rev=1279284780&amp;do=diff</link>
        <description>This article is about numerical rounding, more specific, about implementing the tie-breaking technique called “round-to-even” using MyHDL. There is a good article about Numerical Rounding on Wikipedia for reference.

The idea about the tie-breaking technique round-to-even is, to round a fractional number to the nearest even, in case the tie 0.500 appears. So the value 3.5 will be rounded to the integer number 4 and 2.5 will be rounded to the integer 2. A tie is considered the fractional part 0.5…</description>
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        <dc:date>2010-07-16T07:49:22-05:00</dc:date>
        <dc:creator>Guenter Dannoritzer</dc:creator>
        <title>projects:sidebar - Added link to rounding page</title>
        <link>http://www.myhdl.org/doku.php/projects:sidebar?rev=1279284562&amp;do=diff</link>
        <description>*  Welcome to MyHDL

	*  Users &amp; Projects
		*  Thomas Traber
			*  How to connect eispice and MyHDL
			*  Cordic Calculations
			*  Sine Wave Generator using Sigma Delta DAC
			*  Cosimulation using Quartus Simulator
			*  Interactive Simulation with IPython</description>
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        <dc:date>2010-07-16T06:25:18-05:00</dc:date>
        <dc:creator>Guenter Dannoritzer</dc:creator>
        <title>Users &amp; Projects - Added link to page about rounding</title>
        <link>http://www.myhdl.org/doku.php/projects:intro?rev=1279279518&amp;do=diff</link>
        <description>This page lists a number of MyHDL users and projects. The best thing you can do to support MyHDL is to add your project here and let people know about it!

Request an account

Dillon Engineering


Dillon Engineering uses MyHDL in its verification flow. Read more
about it here.</description>
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        <dc:date>2010-07-03T17:22:10-05:00</dc:date>
        <dc:creator>Jan Decaluwe</dc:creator>
        <title>MyHDL 0.7</title>
        <link>http://www.myhdl.org/doku.php/dev:0.7?rev=1278195730&amp;do=diff</link>
        <description>Requirement: Python 2.6.

New features, done in development:


	*  deprecated compiler package -&gt; ast package to prepare for the future.
	*  shadow signals and applications
	*  better support of list of signals in always_comb
	*  doc strings in output, both “official” and other ones
	*  new options to control Verilog output
	*  docstrings to conversion output, both official and non-official ones
	*  support for ternary operator in conversion, requires VHDL 2008 within processes
	*  use __index__…</description>
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        <dc:date>2010-06-22T02:22:33-05:00</dc:date>
        <dc:creator>Jan Decaluwe</dc:creator>
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        <description>MyHDL uses the standard Python distutils package for distribution and installation. This page contains detailed instructions for installing MyHDL on a typical Linux or Unix system. For other platforms, you have to follow an equivalent procedure. Remember that MyHDL can be installed on any platform that supports Python. For more information about installing on non-Linux platforms such as Windows, read about
 Installing Python Modules.</description>
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        <dc:date>2010-06-21T11:32:30-05:00</dc:date>
        <dc:creator>Jan Decaluwe</dc:creator>
        <title>dev:sidebar</title>
        <link>http://www.myhdl.org/doku.php/dev:sidebar?rev=1277137950&amp;do=diff</link>
        <description>*  Welcome to MyHDL

	*  The Development Zone
		*  Introduction
		*  Source code repository
		*  Contributing changesets
		*  Development snapshots
		*  Open tasks
		*  MyHDL 0.7
		*  Ideas and Draft Proposals
			*  myhdl.org
			*  VHDL Cosimulation with GHDL</description>
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        <dc:date>2010-06-21T11:13:43-05:00</dc:date>
        <dc:creator>Jan Decaluwe</dc:creator>
        <title>Frequently Asked Questions</title>
        <link>http://www.myhdl.org/doku.php/faq?rev=1277136823&amp;do=diff</link>
        <description>Modeling

What is the default bit width of an intbv object?


By default, an intbv object has an “indefinite” bit width. Although this is a novel concept compared to traditional HDL modeling, it corresponds to the natural way to think about integers and their 2's complement representation. Consider:</description>
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