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        <title>MyHDL meps</title>
        <description></description>
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       <dc:date>2010-09-10T07:28:54-05:00</dc:date>
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        <title>MyHDL</title>
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        <dc:date>2006-10-19T08:57:17-05:00</dc:date>
        <title>Introduction</title>
        <link>http://www.myhdl.org/doku.php/meps:intro?rev=1161266237&amp;do=diff</link>
        <description>These pages document the MyHDL Enhancement Proposals (MEPs) and their status.</description>
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        <dc:date>2007-04-18T15:14:07-05:00</dc:date>
        <title>Creating generators with decorators</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-100?rev=1176927247&amp;do=diff</link>
        <description>MEP:  100            Author:  Jan Decaluwe            Status:  Final           Created:  19-Oct-2005     MyHDL-Version:  0.5 
Background


Python 2.4 introduced a new feature called decorators. A decorator consists of special syntax in front of a function declaration. It refers to a decorator function. The decorator function automatically transforms the declared function into some other callable object.</description>
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        <dc:date>2007-04-18T15:14:29-05:00</dc:date>
        <title>User-defined Verilog code</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-101?rev=1176927269&amp;do=diff</link>
        <description>MEP:  101            Author:  Jan Decaluwe            Status:  Final           Created:  9-Nov-2005     MyHDL-Version:  0.5 
Background


In order to provide a path to implementation, MyHDL code can be converted to Verilog. However, in some cases the conversion may fail or the result may not be acceptable. For example:</description>
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        <dc:date>2007-05-07T13:41:16-05:00</dc:date>
        <title>myhdl.org</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-102?rev=1178563276&amp;do=diff</link>
        <description>MEP:  102            Author:  Jan Decaluwe            Status:             Created:       MyHDL-Version:  Undefined 

This space is reserved for a proposal for a MyHDL web site. The draft is being developed here.</description>
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        <dc:date>2009-06-19T16:02:08-05:00</dc:date>
        <title>Tristate and bidirectional signals</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-103?rev=1245445328&amp;do=diff</link>
        <description>MEP:  103            Author:  Jan Decaluwe            Status:  Draft           Created:  May 10, 2007     MyHDL-Version:   
Background


In the author's opinion, there is almost never a good reason to
use on-chip tristates. Tristates often create problems related to reliability,
power consumption and testability. Furthermore, a better implementation of
the required functionality can usually be
found with standard CMOS logic. The only true advantage of tristates
is to save on pins and routing wir…</description>
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        <dc:date>2008-07-10T02:23:22-05:00</dc:date>
        <title>Get rid of the Signal</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-104?rev=1215674602&amp;do=diff</link>
        <description>MEP:  104            Author:  Thomas Traber            Status:  Draft           Created:  June 11, 2008     MyHDL-Version:   




Often Signals as seperate entities are not needed.

Assume we have a functional block datasource and a block datasink.</description>
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        <dc:date>2009-06-23T03:42:28-05:00</dc:date>
        <title>Shadow signals</title>
        <link>http://www.myhdl.org/doku.php/meps:mep-105?rev=1245746548&amp;do=diff</link>
        <description>MEP:  105            Author:  Jan Decaluwe            Status:  Draft           Created:  June 19, 2009    MyHDL-Version:   
Introduction


Compared to mainstream HDLs, MyHDL signals are less flexible. For example, slicing a signal returns a slice of the current value. For behavioral code, this is just fine. However, it implies that you cannot use such as slice in structural descriptions. In other words, a signal slice cannot be used as a signal. Obviously, this behavior is restrictive and confus…</description>
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        <dc:date>2009-06-19T16:05:18-05:00</dc:date>
        <title>meps:sidebar</title>
        <link>http://www.myhdl.org/doku.php/meps:sidebar?rev=1245445518&amp;do=diff</link>
        <description>*  Welcome to MyHDL 

	*  The Development Zone
		*  MyHDL Enhancement Proposals
			*  Introduction
			*  Creating generators with decorators
			*  User-defined Verilog code
			*  myhdl.org
			*  Tristate and bidirectional signals
			*  Shadow signals</description>
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