Examples

Jump right in with MyHDL examples. Consult the Manual when needed.

Flip-flops and Latches

modelling and simulating small sequential devices
waveform viewing
automatic conversion to Verilog or VHDL

Johnson Counter

modelling a counter
writing a test bench for the counter and simulating it
automatic conversion to Verilog

StopWatch

writing a unit test before the implementation
using py.test as a unit test framework
coding a hierarchical design
coding for ROM inference
synthesis of the output Verilog code

Cordic-based Sine Computer

using the intbv class to model negative numbers
using conversion to handle the details of signed and unsigned representations
taking advantage of the elaboration phase for conversion
using co-simulation to verify the output Verilog code

Bitonic Sort

writing structural MyHDL code using recursion and lists of signals
using a reference software implementation

Hello World

the advantages of MyHDL integer arithmetic
embedded scripting in convertible code